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ya we cs guys......rulz......our collg.........& we got the "ROYAL CS" ya baby.......we rockz

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i wish all friends of CEMP happy dewali!

intel 8085 architechture at a glance

Intel 8085
Central processing unit

An Intel 8085AH processor.
Produced	From 1977 to 1990s
Common manufacturer(s)	Intel and several others
Max CPU clock	3,5 and 6 MHz
Instruction set	pre x86
Package(s)	40 pin DIP

Memory

Program, data and stack memories occupy the same memory space. The total addressable memory size is 64 KB.

Program memory - program can be located anywhere in memory. Jump, branch and call instructions use 16-bit addresses, i.e. they can be used to jump/branch anywhere within 64 KB. All jump/branch instructions use absolute addressing.

Data memory - the processor always uses 16-bit addresses so that data can be placed anywhere.

Stack memory is limited only by the size of memory. Stack grows downward.

First 64 bytes in a zero memory page should be reserved for vectors used by RST instructions.

Interrupts

The processor has 5 interrupts. They are presented below in the order of their priority (from lowest to highest):

INTR is maskable 8080A compatible interrupt. When the interrupt occurs the processor fetches from the bus one instruction, usually one of these instructions:

• One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into stack and branches to memory location N * 8 (where N is a 3-bit number from 0 to 7 supplied with the RST instruction).
• CALL instruction (3 byte instruction). The processor calls the subroutine, address of which is specified in the second and third bytes of the instruction.

RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 2Ch (hexadecimal) address.

RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 34h (hexadecimal) address.

RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 3Ch (hexadecimal) address.

Trap is a non-maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 24h (hexadecimal) address.

All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM instruction.

I/O ports

256 Input ports
256 Output ports

Registers

Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store operations.

Flag is an 8-bit register containing 5 1-bit flags:

• Sign - set if the most significant bit of the result is set.
• Zero - set if the result is zero.
• Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result.
• Parity - set if the parity (the number of set bits in the result) is even.
• Carry - set if there was a carry during addition, or borrow during subtraction/comparison.

General registers:

• 8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a pair the C register contains low-order byte. Some instructions may use BC register as a data pointer.
• 8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a pair the E register contains low-order byte. Some instructions may use DE register as a data pointer.
• 8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a pair the L register contains low-order byte. HL register usually contains a data pointer used to reference memory addresses.

Stack pointer is a 16 bit register. This register is always incremented/decremented by 2.

Program counter is a 16-bit register.

Instruction Set

8085 instruction set consists of the following instructions:

• Data moving instructions.
• Arithmetic - add, subtract, increment and decrement.
• Logic - AND, OR, XOR and rotate.
• Control transfer - conditional, unconditional, call subroutine, return from subroutine and restarts.
• Input/Output instructions.
• Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations, etc.

Addressing modes

Register - references the data in a register or in a register pair.
Register indirect - instruction specifies register pair containing address, where the data is located.
Direct.
Immediate - 8 or 16-bit data.

The Intel 8085 is an 8-bit microprocessor introduced by Intel in 1977. It was binary-compatible with the more-famous Intel 8080 but required less supporting hardware, thus allowing simpler and less expensive microcomputer systems to be built.

The "5" in the model number came from the fact that the 8085 required only a +5-volt (V) power supply rather than the +5V, -5V and +12V supplies the 8080 needed. Both processors were sometimes used in computers running the CP/M operating system, and the 8085 later saw use as a microcontroller (much by virtue of its component count reducing feature). Both designs were eclipsed for desktop computers by the compatible but more capable Zilog Z80, which took over most of the CP/M computer market as well as taking a large share of the booming home computer market in the early-to-mid-1980s. The 8085 had a very long life as a controller. Once designed into such products as the DECtape controller and the VT100 video terminal in the late 1970s, it continued to serve for new production throughout the life span of those products (generally many times longer than the new manufacture lifespan of desktop computers).

Ban on mobile phone: Managment takes action

Management begin to take action regarding ban of mobile phones in the campus.Around 10 phones has been captured from the students as they are said to have used it in the class.But the students strongly opposes the statement and said that authorities are simply making a show.

Topic of the week (22 oct 2008)

Capacitors and charging

The voltage on a capacitor depends on the amount of charge you store on its plates. The current flowing onto the positive capacitor plate (equal to that flowing off the negative plate) is by definition the rate at which charge is being stored. So the charge Q on the capacitor equals the integral of the current with respect to time. From the definition of the capacitance,

v_C = q/C, so

Now remembering that the integral is the area under the curve (shaded blue), we can see in the next animation why the current and voltage are out of phase.

Once again we have a sinusoidal current i = I_m . sin (ωt), so integration gives

(The constant of integration has been set to zero so that the average charge on the capacitor is 0).

Now we define the capacitive reactance X_C as the ratio of the magnitude of the voltage to magnitude of the current in a capacitor. From the equation above, we see that X_C = 1/ωC. Now we can rewrite the equation above to make it look like Ohm's law. The voltage is proportional to the current, and the peak voltage and current are related by

V_m = X_C.I_m.

Note the two important differences. First, there is a difference in phase: the integral of the sinusoidal current is a negative cos function: it reaches its maximum (the capacitor has maximum charge) when the current has just finished flowing forwards and is about to start flowing backwards. Run the animation again to make this clear. Looking at the relative phase, the voltage across the capacitor is 90°, or one quarter cycle, behind the current. We can see also see how the φ = 90° phase difference affects the phasor diagrams at right. Again, the vertical component of a phasor arrow represents the instantaneous value of its quanitity. The phasors are rotating counter clockwise (the positive direction) so the phasor representing V_C is 90° behind the current (90° clockwise from it).

Recall that reactance is the name for the ratio of voltage to current when they differ in phase by 90°. (If they are in phase, the ratio is called resistance.) Another difference between reactance and resistance is that the reactance is frequency dependent. From the algebra above, we see that the capacitive reactance X_C decreases with frequency . This is shown in the next animation: when the frequency is halved but the current amplitude kept constant, the capacitor has twice as long to charge up, so it generates twice the potential difference. The blue shading shows q, the integral under the current curve (light for positive, dark for negative). The second and fourth curves show V_C = q/C . See how the lower frequency leads to a larger charge (bigger shaded area before changing sign) and therefore a larger V_C.

Thus for a capacitor, the ratio of voltage to current decreases with frequency. We shall see later how this can be used for filtering different frequencies.

(SOURCE:http://www.physclips.unsw.edu.au/~jw/AC.html)

Last round seats filled!

Today (18-10-08) all the remaining seats ( 14 in IT and 3 In EEE) , which were vacant after all the allotments , except those of the seats owned by government were filled today . Many students who have alredy given applictions and those who came on seeing the advertisemnt given by the management appeared for the interview. The list of alloted students based on the marks and ranks were announced by 2'O clock afternoon. The fourth phase allottment for the govt seats are to be published Click the following link for the official website of CEE.

http://www.cee.kerala.gov.in/keam/main/indexcap.php?dstr=

	IMPORTANT NOTICE:
Candidates who do not want any further allotment should delete their higher options before 5 PM on 18/10/2008

moblie phones banned

mobile phones banned in college of engineering and managment punnapra.
what you think about this? commet..

Topic of the WEEK

Direct Mapping

This is the simplest among the three techniques. Its simplicity
stems from the fact that it places an incoming main memory block into a specific
fixed cache block location. The placement is done based on a fixed relation between
the incoming block number, i, the cache block number, j, and the number of cache
blocks, N:
j = i mod N

According to the direct-mapping technique the MMU interprets the address issued
by the processor by dividing the address into three fields as shown in Figure below:






The lengths, in bits, of each of the fields in Figure are:
1. Word field = log2 B, where B is the size of the block in words.
2. Block field = log2 N, where N is the size of the cache in blocks.
3. Tag field = log2 (M/N), where M is the size of the main memory in blocks.
4. The number of bits in the main memory address = log2 (B x M)
It should be noted that the total number of bits as computed by the first three
equations should add up to the length of the main memory address. This can be
used as a check for the correctness of your computation.

(extracted from book:FUNDAMENTALS OF COMPUTER ORGANIZATION AND ARCHITECTURE by Mostafa Abd-El-Barr & Hesham El-Rewini )

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Computer Architecture and Organization

http://www.eng.wayne.edu
lecture notes
http://www.ece.eng.wayne.edu/~gchen/ece4680/lecture-notes/lecture-notes.html

Computer Architecture and Organization

My lecture notes are available in Adobe Portable Data Format in 2 different layouts. Keep in mind that the material is prepared to help me teaching, not as your only study material. Effective learning requires reading the textbook, attending classes, looking at my class materials and adding your own notes to the class materials.

The materials presented are primarily created for my presentation in the classroom and thus cannot replace the book. They may help you in following the class and get a better feeling on which topics I have covered more deeply and which topics I put aside. Please let me know whenever you find errors in the materials.

My lecture notes are based on the early version of David Patterson. Due to copyright reasons these materials can only be used for educational purposes in conjunction with the textbook. Permission for commercial purposes should be obtained from the original copyright holder and the successive copyright holders including me. 

Lecture notes (in PDF formats)

• Overview (pdf-2 or pdf-6)
• Performance Evaluation (pdf-2 or pdf-6)
• Instruction Set Architecture (pdf-2 or pdf-6)
• MIPS ISA: An Example (pdf-2 or pdf-6)
• ALU Design I: Basic (pdf-2 or pdf-6)
• ALU Design II: Multiplication (pdf-2 or pdf-6)
• ALU Design III: Divide and Floating Point (pdf-2 or pdf-6)

• Midterm Review (pdf-2)

• Datapath Design: Single Cycle Implementation, Part I (pdf-2 or pdf-6 or pdf-notes )
• Control Design: Single Cycle Implementation, Part II (pdf-2 or pdf-6 or pdf-notes)
• Datapath Design: Multiple Cycle Implementation, Part I (pdf-2 or pdf-6 or pdf-notes)
• Control Design: Multiple Cycle Implementation, Part II ( Skipped )
• Pipelining, Part I (pdf-2 or pdf-6 or pdf-notes)
• Pipelining, Part II (pdf-2 or pdf-6)
• Memory Hierarchy: Overview (pdf-2 or pdf-6)
• Memory Hierarchy: Cache System (pdf-2 or pdf-6)
• Memory Hierarchy: Virtual Memory System (pdf-2 or pdf-6)
• Input/Output System: Bus (pdf-2 or pdf-6)
• Input/Output System: Role of Operating System (pdf-2 or pdf-6)
• Final Review (pdf)

¡¡Notes: pdf-2 lays out 2 slides per page; pdf-6 lays out 6 slides per page; pdf-notes contains detailed explanations.

social works

do anybody have more photos plz sent to me:jkuttu@gmail.com i'm christy [branch---cse]